By Himanshu Bhatnagar
Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® describes the complicated strategies and methods used for ASIC chip synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. furthermore, the whole ASIC layout stream technique certain for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this publication is on real-time software of Synopsys instruments used to wrestle numerous difficulties noticeable at VDSM geometries. Readers might be uncovered to a good layout method for dealing with advanced, sub-micron ASIC designs. importance is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT test insertion, hyperlinks to format, and static timing research. At each one step, difficulties concerning every one part of the layout circulate are pointed out, with strategies and work-arounds defined intimately. furthermore, an important matters on the topic of structure, consisting of clock tree synthesis and back-end integration (links to structure) also are mentioned at size. additionally, the publication comprises in-depth discussions at the fundamentals of Synopsys expertise libraries and HDL coding kinds, distinct in the direction of optimum synthesis strategies.
Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® is meant for a person who's concerned about the ASIC layout technique, ranging from RTL synthesis to ultimate tape-out. aim audiences for this e-book are training ASIC layout engineers and graduate scholars project complex classes in ASIC chip layout and DFT options.
From the Foreword:
`This e-book, written by means of Himanshu Bhatnagar, presents a complete evaluate of the ASIC layout move exact for VDSM applied sciences utilizing the Synopsis suite of instruments. It emphasizes the sensible concerns confronted by way of the semiconductor layout engineer by way of synthesis and the combination of front-end and back-end instruments. conventional layout methodologies are challenged and specific recommendations are provided to assist outline the subsequent iteration of ASIC layout flows. the writer offers a number of sensible examples derived from real-world events that may end up invaluable to working towards ASIC layout engineers in addition to to scholars of complicated VLSI classes in ASIC design'.
Dr Dwight W. Decker, Chairman and CEO, Conexant platforms, Inc., (Formerly, Rockwell Semiconductor Systems), Newport seashore, CA, USA.
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Extra info for Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ and PrimeTime®
The following command may be used to update the technology library present in DC 's memory to reflect the new custom wire-load models. txt Let's assume that the design has been re-analyzed and is now passing both setup and hold-time requirements. The next step is to detail route the design. This is a layout dependent feature , therefore will not be discussed here. 5 Post-Layout Steps The post-layout steps involve, verifying the design for timing with actual delays back annotated; functional simulation of the design; and lastly, performing LVS and DRC .
Lets assume that you have successfully synthesized three sub-blocks, namely tap_bypass, tapfnstruction and tap_state. v file. Also, the wire-load mode may need to be changed to enclosed for proper modeling of the interconnect wires. Since the sub-modules contain the TUTORIAL 21 dont_touch attribute, the top-level synthesis will not optimize across boundaries, and may violate the design rule constraints. To remove these violations, you must re-synthesize/optimize the design with the dont_touch attribute removed from the sub-blocks.
2 tck The following script uses the above commands and may be used to generate the pre-layout SDF for the tap_controller design. This SDF file is targeted for simulating the design dynamically with timing . In addition, the script also generates the timing constraints file. Though this file is also in SDF format, it is solely used for forward annotating the timing information to the layout tool in order to perform timing driven layout. 4 Verification The final step before layout is to verify the structural netlist for functionality.